Messages in this thread | | | Date | Thu, 21 Feb 2008 10:52:33 +0900 (JST) | Subject | Re: [PATCH] atmel_spi: support zero length transfer | From | Atsushi Nemoto <> |
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On Wed, 20 Feb 2008 18:55:01 +0100, Marc Pignat <marc.pignat@hevs.ch> wrote: > > A spi transfer with zero length is not invalid. Such transfer can be > > used to achieve delay before first CLK edge after chipselect assertion. > How long will be that delay?
My funny custom device requires 100us or so. Unfortunately atmel_spi can not use such a slow bitrate.
> If they are really users of that kind of thing, this should be fixed by adding > a "delay_us_before_xfer" field in the struct spi_transfer.
Yes, it would be an another way to achieve it. But as long as zero length transfer is legal on this API, I don't want to add other fields.
> Have you tested it? I think if you start a transfer with 0 len, the ENDRX bit > will never rise, however, I'm not sure about this.
Yes. I tested it on AT91SAM9260 and it seems ENDRX rises soon. Though it can be possible to avoid starting DMA for zero length transfer, I think it is not worth to optimize for such a rare case.
--- Atsushi Nemoto
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