Messages in this thread |  | | | Date | Tue, 19 Feb 2008 11:42:46 -0800 | | From | "Siddha, Suresh B" <> | | Subject | Re: Unable to continue testing of 2.6.25 |
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On Mon, Feb 18, 2008 at 11:18:48AM -0800, Roland Dreier wrote: > > > AFAIK mapping PCI memory WB is not allowed, so WC is really our only > > > choice. > > > afaik that depends on the BAR being prefetchable or not. > > In my case the BAR is prefetchable.
Even if the BAR is prefetchable, on some platforms mapping MMIO space as WB can cause bad results like machine check etc.
> > (and by your argument, ioremap_cached() would not be useful, and since that was, until > > 2.6.25-rc1, the default behavior for ioremap(), would have caused massive problems) > > I'm not sure what ioremap_cached() would really do in my case, since > the MTRRs for PCI memory are set to UC, so without monkeying with MTRR > contents (which can't really be done safely) the only choices we have > are leaving the mapping as UC or using PAT to get WC.
thanks, suresh
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