Messages in this thread |  | | | Subject | Re: [ofa-general] Re: Demand paging for memory regions | | From | Roland Dreier <> | | Date | Tue, 12 Feb 2008 14:41:48 -0800 |
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> > Chelsio's T3 HW doesn't support this.
> Not so far I guess but it could be equipped with these features right?
I don't know anything about the T3 internals, but it's not clear that you could do this without a new chip design in general. Lot's of RDMA devices were designed expecting that when a packet arrives, the HW can look up the bus address for a given memory region/offset and place the packet immediately. It seems like a major change to be able to generate a "page fault" interrupt when a page isn't present, or even just wait to scatter some data until the host finishes updating page tables when the HW needs the translation.
- R.
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