Messages in this thread | | | Date | Wed, 3 Dec 2008 10:02:18 +0100 | From | Ingo Molnar <> | Subject | Re: [PATCH] x86: fix broken flushing in GART nofullflush path |
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u * Joerg Roedel <joro@8bytes.org> wrote:
> On Tue, Dec 02, 2008 at 08:27:59PM +0100, Ingo Molnar wrote: > > > > * Joerg Roedel <joerg.roedel@amd.com> wrote: > > > > > In the non-default nofullflush case the GART is only flushed when > > > next_bit wraps around. But it can happen that an unmap operation unmaps > > > memory which is behind the current next_bit location. If these addresses > > > are reused it may result in stale GART IO/TLB entries. Fix this by > > > setting the GART next_bit always behind an unmapped location. > > > > > > Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> > > > --- > > > arch/x86/kernel/pci-gart_64.c | 2 ++ > > > 1 files changed, 2 insertions(+), 0 deletions(-) > > > > applied to tip/x86/iommu, thanks Joerg! > > > > a stale iotlb should not cause any problems in this particular GART case, > > right? It might be a security leak in a security-domain enforcing iotlb > > case, but the GART is a DMA bouncing helper in essence. Can you see any > > failure mode of this bug? > > It can cause data corruption because the GART redirects the IO to a > wrong address because of a stale entry in its TLB. I found this bug > after I fixed the same issue in the AMD IOMMU code (commit 80be308d). > > The reason this was not found earlier is that lazy flushing is not the > default in GART. But I didn't try to trigger the bug.
ah, indeed. The stale entries themselves are not an issue - the problem is reuse: if a stale entry is reused but then we do not flush, we can get data corruption. I've cherry-picked it over into x86/urgent as well.
Ingo
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