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    SubjectIntel x86_64 llc_shared_map/cpu_llc_id anomolies
    I'm seeing some behavior on a multiblade Intel x86_64 that does not
    appear to be correct.

    My x86_64 multiblade configuration has llc_shared_map (last level
    cache shared map) showing cpus on different blades sharing a last
    level cache. With 2 cpus/blade and 4 blades (8 cpus total), I show
    cpus 1,3,5,7 sharing llc, and 0,2,4,6 sharing llc.

    The llc_shared_map is set based on matching values of cpu_llc_id
    (last level cache ID). The cpu_llc_id is set based on
    cpuinfo_x86->apicid. This value is set to cpuinfo_x86->initial_apicid.

    The value of cpuinfo_x86->initial_apicid appears to be set twice
    during startup:

    - In generic_identify(), using the value returned by cpuid_ebx(1).
    This is the initial_apicid set at poweron, and results in
    cpuinfo_x86->initial_apicid having a value that is not unique across
    blades (where the blades do not share a cpu bus).

    - Later, in detect_extended_topology() using the value for edx returned
    by cpuid_count(0xb,..). This results in cpuinfo_x86->initial_apicid
    having a value that appears to be unique across blades.

    Between those two assignments, cpuinfo_x86->apicid is set to
    cpuinfo_x86->initial_apicid, so it is non-unique. Then cpu_llc_id gets
    set in init_intel_cacheinfo(), so cpu_llc_id winds up with a value that
    is non-unique across blades, and llc_shared_map winds up showing cpus
    on different blades as sharing last level cache.

    Is cpu_llc_id supposed to be unique across blades? I assume
    llc_shared_map should not be showing shared cache across blades.

     \ /
      Last update: 2008-12-12 22:45    [W:0.028 / U:0.188 seconds]
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