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Needed by architecture-independant tsc-sync.c. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> CC: Ralf Baechle <ralf@linux-mips.org> CC: Peter Zijlstra <a.p.zijlstra@chello.nl> --- arch/mips/include/asm/barrier.h | 6 ++++++ 1 file changed, 6 insertions(+) Index: linux.trees.git/arch/mips/include/asm/barrier.h =================================================================== --- linux.trees.git.orig/arch/mips/include/asm/barrier.h 2008-10-30 20:22:49.000000000 -0400 +++ linux.trees.git/arch/mips/include/asm/barrier.h 2008-11-07 00:16:28.000000000 -0500 @@ -152,4 +152,10 @@ #define smp_llsc_rmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") #define smp_llsc_wmb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory") +/* + * MIPS does not have any instruction to serialize instruction execution on the + * core. + */ +#define sync_core() + #endif /* __ASM_BARRIER_H */ -- Mathieu Desnoyers OpenPGP key fingerprint: 8CD5 52C3 8E3C 4140 715F BA06 3F25 A8FE 3BAE 9A68 | ||||||||||||
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