Messages in this thread | | | Date | Tue, 04 Nov 2008 10:14:11 -0800 | From | "H. Peter Anvin" <> | Subject | Re: [PATCH RFC/RFB] x86_64, i386: interrupt dispatch changes |
| |
Alexander van Heukelum wrote: > > That's good to know. I assume this LOCKed bus cycle only occurs > if the (hidden) segment information is not cached in some way? > How many segments are typically cached? In particular, does it > optimize switching between two segments? >
Yes, there is a segment descriptor cache (as opposed to the hidden but architectural segment descriptor *registers*, which the Intel documentation confusingly call a "cache".)
It is used to optimize switching between a small number of segments, and was crucial for decent performance on Win9x, which contained a bunch of 16-bit code.
-hpa
| |