Messages in this thread | | | From | Frans Pop <> | Subject | Re: [2.6.28-rc5] TSC sync error and high hrtimer_start (was: Bootup time regression from 2.6.27 to 2.6.28-rc3+) | Date | Mon, 17 Nov 2008 03:18:22 +0100 |
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On Sunday 16 November 2008, Frans Pop wrote: > Possibly this may be related to this diff in the boot messages: > -checking TSC synchronization [CPU#0 -> CPU#1]: passed. > +checking TSC synchronization [CPU#0 -> CPU#1]: > +Measured 696 cycles TSC warp between CPUs, turning off TSC clock. > +Marking TSC unstable due to check_tsc_sync_source failed > > With .27.4 TSC _always_ passed. Now, with .28-rc5 I get this warp. I've > done two boots so far, for the other one the warp was 680 cycles.
Maybe this extra context a bit earlier in dmesg is relevant here:
-Calibrating delay loop (skipped), value calculated using timer frequency.. 6399.76 BogoMIPS (lpj=12799520) +HPET: 3 timers in total, 0 timers will be used for per-cpu timer +Calibrating delay loop (skipped), value calculated using timer frequency.. 6399.73 BogoMIPS (lpj=12799476) [...] -ACPI: Core revision 20080609 +ACPI: Core revision 20080926 +Setting APIC routing to flat ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 CPU0: Intel(R) Pentium(R) D CPU 3.20GHz stepping 07 -Using local APIC timer interrupts. -APIC timer calibration result 12499520 -Detected 12.499 MHz APIC timer. -Booting processor 1/1 ip 6000 +Booting processor 1 APIC 0x1 ip 0x6000 Initializing CPU#1 -Calibrating delay using timer specific routine.. 6399.94 BogoMIPS (lpj=12799898) +Calibrating delay using timer specific routine.. 6198.05 BogoMIPS (lpj=12396107)
Note the rather large difference in BogoMIPS between core 0 and 1.
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