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SubjectRe: [PATCH] oprofile: re-arm APIC_DM_NMI in ppro_check_ctrs()
Andi Kleen a écrit :
>> oprofile_add_sample(regs, i);
>> + /*
>> + * We need to unmask the apic vector *before*
>> + * writing reset_value to msr counter
>> + */
>> + apic_write(APIC_LVTPC, APIC_DM_NMI);
>> wrmsrl(msrs->counters[i].addr, -reset_value[i]);
>> }
>> }
>>
>> - /* Only P6 based Pentium M need to re-unmask the apic vector but it
>> - * doesn't hurt other P6 variant */
>> - apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
>
> Did you also test if it really needs to be inside the if () or
> just before the wrmsrl?
>

Andi, the following patch also works well for me. The key is we must
unmask APIC before the wrmsrl. after/before the rdmsrl has no impact.

I wonder then if the final comment in ppro_check_ctrs() is still applicable.


PATCH] oprofile: un-mask APIC before resetting counter in ppro_check_ctrs()

While using oprofile on my HP BL460c G1, (two quad core intel E5450 CPU),
I noticed that one CPU after the other could not get anymore NMI.

After a while, all cores where blocked (ie not generating events for oprofile)
I tried all major linux versions and all where affected by this freeze.

I found that we have to un-mask APIC *before* writing to MSR counter
when we get event notification, because we use APIC_LVTPC in edge triggered mode.

Signed-off-by: Eric Dumazet <dada1@cosmosbay.com>
---
arch/x86/oprofile/op_model_ppro.c | 10 ++++++----
1 files changed, 6 insertions(+), 4 deletions(-)diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 3f1b81a..8484528 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -126,6 +126,12 @@ static int ppro_check_ctrs(struct pt_regs * const regs,
u64 val;
int i;

+ /*
+ * We need to unmask the apic vector *before* writing reset_value
+ * to msr counter, because we use edge trigger
+ */
+ apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
+
for (i = 0 ; i < num_counters; ++i) {
if (!reset_value[i])
continue;
@@ -136,10 +142,6 @@ static int ppro_check_ctrs(struct pt_regs * const regs,
}
}

- /* Only P6 based Pentium M need to re-unmask the apic vector but it
- * doesn't hurt other P6 variant */
- apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
-
/* We can't work out if we really handled an interrupt. We
* might have caught a *second* counter just after overflowing
* the interrupt for this counter then arrives
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