Messages in this thread |  | | | Subject | Re: [PATCH] fix compile breakage caused by 2ae111cdd8d83ebf9de72e36e68a8c84b6ebbeea | | From | James Bottomley <> | | Date | Fri, 31 Oct 2008 12:52:02 -0500 |
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On Thu, 2008-10-30 at 23:06 +0100, Ingo Molnar wrote: > * James Bottomley <James.Bottomley@HansenPartnership.com> wrote: > > > >From bd011c0cc51ce1fbab95403a570a8b47ad6ba500 Mon Sep 17 00:00:00 2001 > > From: James Bottomley <James.Bottomley@HansenPartnership.com> > > Date: Wed, 29 Oct 2008 11:19:49 -0500 > > Subject: [VOYAGER] x86: Fix subarch compile breakage > > > > commit 2ae111cdd8d83ebf9de72e36e68a8c84b6ebbeea > > Author: Cyrill Gorcunov <gorcunov@gmail.com> > > Date: Mon Aug 11 18:34:08 2008 +0400 > > > > x86: apic interrupts - move assignments to irqinit_32.c, v2 > > > > Wrongly moved irq2 setup out of the mach-default/setup.c file. This > > causes a breakage on voyager which needs its own version. Fix by > > moving it back again. > > > > Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com> > > --- > > arch/x86/kernel/irqinit_32.c | 12 ------------ > > arch/x86/mach-default/setup.c | 12 ++++++++++++ > > 2 files changed, 12 insertions(+), 12 deletions(-) > > > > diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c > > index 845aa98..3928784 100644 > > --- a/arch/x86/kernel/irqinit_32.c > > +++ b/arch/x86/kernel/irqinit_32.c > > @@ -81,15 +81,6 @@ void __init init_ISA_irqs (void) > > } > > } > > > > -/* > > - * IRQ2 is cascade interrupt to second interrupt controller > > - */ > > -static struct irqaction irq2 = { > > - .handler = no_action, > > - .mask = CPU_MASK_NONE, > > - .name = "cascade", > > -}; > > - > > DEFINE_PER_CPU(vector_irq_t, vector_irq) = { > > [0 ... IRQ0_VECTOR - 1] = -1, > > [IRQ0_VECTOR] = 0, > > @@ -167,9 +158,6 @@ void __init native_init_IRQ(void) > > alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt); > > #endif > > > > - if (!acpi_ioapic) > > - setup_irq(2, &irq2); > > - > > /* setup after call gates are initialised (usually add in > > * the architecture specific gates) > > */ > > diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c > > index 37b9ae4..53b4202 100644 > > --- a/arch/x86/mach-default/setup.c > > +++ b/arch/x86/mach-default/setup.c > > @@ -38,6 +38,15 @@ void __init pre_intr_init_hook(void) > > init_ISA_irqs(); > > } > > > > +/* > > + * IRQ2 is cascade interrupt to second interrupt controller > > + */ > > +static struct irqaction irq2 = { > > + .handler = no_action, > > + .mask = CPU_MASK_NONE, > > + .name = "cascade", > > +}; > > + > > /** > > * intr_init_hook - post gate setup interrupt initialisation > > * > > @@ -53,6 +62,9 @@ void __init intr_init_hook(void) > > if (x86_quirks->arch_intr_init()) > > return; > > } > > + if (!acpi_ioapic) > > + setup_irq(2, &irq2); > > + > > } > > hm, this change looks backwards (doubly so ;-). > > Is the build problem caused by the lack of the acpi_ioapic flag on > Voyager?
Yes, exactly ... and it has no apic or acpi ... I suppose something like this could be used instead.
It would be fixable by stripping the irq2 setup from voyager and directly #including asm/acpi.h in irqinit_32.c, but that would pull in mpspec.h as well, with its associated problems.
an alternative might be to abstract out a explicit_irq2_setup variable and making that be !acpi_ioapic on PC and 1 on voyager.
James
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