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    SubjectRe: ptrace API extensions for BTS

    I looked at your code. My understanding is that it abstracts the BTS
    so that higher
    level code does not have to know the intricacies of the implementation
    given that the changed the DS_AREA structure a lot between P4 and Core 2.

    The code does not cover PEBS though. In the case of perfmon, the ra PEBS data
    is exposed to user-level. This way we ensure zero-copy all the way to
    the application.
    Of course, that means applications needs to know whether they are using P4 PEBS
    or Core PEBS, but that's fine.

    I noticed that your code does not support 64-bit Netburst DS_AREA configuration.
    I have used that myself and it works. Also Penryn support is missing
    (Fam 6 model 23).

    The code does not actually touch the HW resource. This needs to be
    added somehow.
    It must be part of a register allocator outside of ds.c. We could
    extend the simple
    allocator currently used for the PMU registers in perfctr-watchdog.c.
    In fact, that one
    would have to be generalized.

    Perfmon does read/write the DS_AREA pointer and content. PEBS is supported in
    per-thread and system-wide mode. This means that we save/restore DS_AREA pointer
    on ctxsw. Perfmon does not touch the BTS specific fields, just the PEBS relevant
    fields. PEBS does generate interrupts and they are routed via the PMU interrupt.

    Internally perfmon2 needs to access the internals of the ds_area to
    fiddle with the
    pebs_index/pebs_intr_thres. Some of that code is in the perfmon core and not in
    the model specific (P4 vs. Core) kernel module. On Core2, I think I could get
    rid of this dependency but not on P4. I could use your code to abstract the DS
    area and give me access to the pebs fields in a more generic way. that assumes
    you would add PEBS support to ds.c.

    What do you think?


    On Jan 30, 2008 1:52 PM, Metzger, Markus T <> wrote:
    > >From: stephane eranian []
    > >Sent: Mittwoch, 30. Januar 2008 12:01
    > >You can get information about the perfmon2 project at:
    > >
    > I downloaded your patch for 2.6.23 and cloned your git repository.
    > From a first glance, it looks like there is indeed a lot of overlap.
    > >I would like to take a look at your patches. Where can I get them?
    > You can find the changes in the mm branch of the x86 git. Do they keep
    > the patches there, somewhere, as well?
    > You should get the best overview if you look at arch/x86/kernel/ds.c,
    > include/asm-x86/ds.h, include/asm-x86/ptrace-abi.h, and
    > arch/x86/kernel/ptrace.c or simply grep for BTS.
    > I have all the patches that I submitted but they rather protocol
    > development than describe the final thing.
    > >My understanding at this point is that we would need to coordinate
    > >access to the
    > >DS_AREA. It would likely have to be mutually exclusive access.
    > From a brief look at your patch, I would say that we should rather
    > combine the configuration and collection part. They are very similar.
    > We might still want to provide different interfaces on top of it.
    > In particular, I think the ptrace interface is most appropriate for
    > debuggers.
    > >I am planning on
    > >adding support for LBRs in the next few months. But BTS the way it is
    > >currently defined
    > >is useless for performance monitoring. I think this a great debug
    > >feature, though.
    > Debugging was my target;-)
    > >Now, there is some preliminary perf. MSR allocator in the kernel.
    > >However, it does not know
    > >of all available MSRs out there. It focuses on the counters mostly.
    > >Perfmon, oprofile and
    > >the NMI watchdog use it. I think it could be generalized to other MSR
    > >(non-contiguous).
    > >
    > >I would be happy to work with you in refining this MSR allocator.
    > Are you planning to get the perfmon patch into the kernel? Or do you
    > want it to remain a separate patch?
    > In the first case, we should try to merge the features. In the second
    > case, refining the MSR allocator would probably be best.
    > thanks and regards,

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