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SubjectRe: [PATCH 11 of 11] x86: defer cr3 reload when doing pud_clear()
Jeremy Fitzhardinge wrote:
>
>> Now, all of this reminds me of something somewhat messy: if we share
>> the kernel page tables for trampoline page tables, as discussed
>> elsewhere, we HAVE to do a complete, all-tlb-including-global-pages
>> flush after use, since the kernel pages are global and otherwise will
>> stick around. Unlike the permissions pages, there aren't G enable
>> bits on the higher levels, but only for the PTEs themselves.
>
> That wouldn't happen to often though, would it. The identity mapping is
> only interested in a 1:1 view on RAM, and that's not going to change at
> all? Does the TLB cache PAT attributes? Do you need to do a global
> flush after changing a PTE's PAT bits to make sure that all that PTE's
> mappings have a consistent view on memory?
>

You do need to flush *that page* globally, yes.

As far as flushing after using the trampoline pagetables, we're talking
about rare, expensive events here like suspend to ram.

-hpa


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