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    SubjectRe: Intel Memory Ordering White Paper
    Date
    On Saturday 08 September 2007 20:30, Alan Cox wrote:
    > On Sat, 8 Sep 2007 18:54:57 +1000
    >
    > Nick Piggin <nickpiggin@yahoo.com.au> wrote:
    > > On Saturday 08 September 2007 08:26, Jesse Barnes wrote:
    > > > FYI, we just released a new white paper describing memory ordering for
    > > > Intel processors:
    > > > http://developer.intel.com/products/processor/manuals/index.htm
    > > >
    > > > Should help answer some questions about some of the ordering primitives
    > > > we use on i386 and x86_64.
    > >
    > > So, can we finally noop smp_rmb and smp_wmb on x86?
    >
    > Nakked-by: Alan Cox <alan@redhat.com>
    >
    > You can only no-op it on 64bit Intel processors. On 32bit it needs to be
    > conditional on whether your processor family (or back compat for it) as
    > the Pentium Pro has some serious store ordering errata (hence the way it
    > needs lock decb for spin_unlock)

    We already noop smp_wmb on i386 even when CONFIG_X86_PPRO_FENCE.

    I'm not sure if either errata can be solved completely by adding lock ops
    in barrier instructions anyway: they both seem to involve situations where
    there is just a single problematic cacheline in question.
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