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From(Eric W. Biederman)
SubjectRe: [PATCH] trim memory not covered by WB MTRRs
DateFri, 08 Jun 2007 17:13:22 -0600
Jesse Barnes <jesse.barnes@intel.com> writes:


>> - Overlapping MTRRs.
>
> Overlapping should be ok, since that's usually intentional (e.g. one big 
> wb range with a portion of uc space due to another mtrr).

I'm not say overlapping was a bug.  I was saying that you don't handle
overlapping mtrrs in figuring the last cached addresses.  Therefore
when a UC range overlaps a WB range we might thing the last page
in the WB range is cached when it is not.

>> - What happens if we have uncached memory lower down?
>
> Holes definitely aren't dealt with, but then we haven't seen any yet...
>
>>   Except for performance problems I guess that case is relatively
>> harmless. - Is it possible and worth it to amend the e820 map, so it
>> shows the problem area as Reserved or otherwise not usable RAM?
>
> That would be useful, but only if we moved the check to a little 
> earlier, prior to the addition of the active ranges from the e820.  
> Might be a little nicer than adjusting end_pfn, but will ultimately 
> achieve the same thing...

Yes, with perhaps a little more consistency.

Eric
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