Messages in this thread | | | Subject | Re: JIT emulator needs | From | Arjan van de Ven <> | Date | Fri, 22 Jun 2007 07:42:11 -0700 |
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> > > > and these methods also destroy yourself on any machine with a looser > > > > cache coherency between I and D-cache.... > > > > > > > > for all but x86 you pretty much have to do the mprotect() between the > > > > two states to deal with the cache flushing properly... > > > > > > If the instructions to force data write-back and/or to > > > invalidate the instruction cache are priveleged, yes. > > > AFAIK, only ARM is that lame. > > > > and your program executes this on all the cpus in the system?
no I meant that you had to call your userspace instruction on all cpus, so on all-but-arm (from the Intel side I know IA64 needs such a flush, but I'm pretty sure PPC does too)
> I don't recall seeing such code in the libgcc tranpoline > setup for PowerPC. Either it's not required, or this is > a rather popular bug.
I suspect it'll be playing under the assumption that going from "no code" to "code" is fine since the icache is cold.
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