Messages in this thread | | | From | Jesse Barnes <> | Subject | Re: [PATCH] trim memory not covered by WB MTRRs | Date | Tue, 12 Jun 2007 08:39:07 -0700 |
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On Friday, June 8, 2007 4:13:22 Eric W. Biederman wrote: > Jesse Barnes <jesse.barnes@intel.com> writes: > >> - Overlapping MTRRs. > > > > Overlapping should be ok, since that's usually intentional (e.g. > > one big wb range with a portion of uc space due to another mtrr). > > I'm not say overlapping was a bug. I was saying that you don't > handle overlapping mtrrs in figuring the last cached addresses. > Therefore when a UC range overlaps a WB range we might thing the last > page in the WB range is cached when it is not.
Oh right, that might be an issue, but we haven't seen it yet...
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