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SubjectRe: PCIE
On Sat, May 26, 2007 at 05:00:39PM -0700, David Miller wrote:
> From: Grant Grundler <>
> Date: Sat, 26 May 2007 17:55:15 -0600
> > MSI (and MSI-X) vectors are required to be exclusive.
> > I submitted that change to pci.txt last year:
> >
> >
> > and ISTR I've posted that bit of the PCI spec a few years ago.
> > But it probably was to linux-pci mailing list only.
> This requirement only extends to the PCI host controller,
> how that interfaces to the cpu and it's limitations is
> an entirely other matter.

Are they really? The device is generating the transaction on the bus.
The PCI host controller (in general) will be routing that transaction
to wherever the "dest addr" of the MSI lives. It doesn't have to be
in the CPU but it will certainly be a proxy for that CPU if it's not.
We won't care if the proxy only have one IRQ line going to the CPU
as long as the de-muxing of the "data" portion results in a unique
identifier that can be mapped to exactly one interrupt handler.

> > The cpus haven't been using interrupt pins for a long time now.
> > Anything with a Local-xAPIC is already using transactions to
> > signal interrupts even if the OS isn't aware of it.
> I'm not talking about x86, x86_64, et al.
> I'm talking about embedded ARM chips and the like, and yes they
> very possibly will be using PCI-E controllers at some point.

It doesn't matter if it's embedded or not. Trying to share what
is the equivalent to an "edge triggered" interrupt is futile.
MSI "vectors" need to be exclusive.

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