Messages in this thread | | | From | Jesse Barnes <> | Subject | Re: [PATCH] support PCI MCFG space on Intel i915 bridges | Date | Mon, 30 Apr 2007 12:25:21 -0700 |
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On Sunday, April 29, 2007 7:10 pm Robert Hancock wrote: > Jesse Barnes wrote: > > Add support for Intel 915 bridge chips to the new PCI MMConfig > > detection code. Tested and works on my sole 915 based platform (a > > Toshiba laptop). I added register masking per Oliver's suggestion, > > and moved the __init qualifier to after the 'static const char' to > > match Ogawa-san's recent cleanup patches. > > > > Signed-off-by: Jesse Barnes <jesse.barnes@intel.com> > > > > diff --git a/arch/i386/pci/mmconfig-shared.c > > b/arch/i386/pci/mmconfig-shared.c index 747d8c6..1339d31 100644 > > --- a/arch/i386/pci/mmconfig-shared.c > > +++ b/arch/i386/pci/mmconfig-shared.c > > @@ -72,6 +72,26 @@ static const char __init *pci_mmcfg_e7520(void) > > return "Intel Corporation E7520 Memory Controller Hub"; > > } > > > > +static const char __init *pci_mmcfg_intel_915(void) > > +{ > > + u32 pciexbar, len = 0; > > + > > + pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar); > > + > > + /* No enable bit or size field, so assume 256M range is > > enabled. */ + len = 0x10000000U; > > Check the 915 spec more carefully, there is an enable bit, it's in > the DEVEN register offset 54h, the bit is called PCIEXBAREN (bit 31). > If that is not set you should be setting pci_mmcfg_config_num to 0 > and bailing out.
Right, but you patch should obsolete this stuff anyway. I'll test it out in the next few days.
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