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    SubjectRe: enable dual rng on VIA C7
    Dave Jones wrote:
    > On Mon, Nov 26, 2007 at 06:02:39PM +0100, Udo van den Heuvel wrote:
    >
    > > I did not know we are already that far ;-)
    > > I mean: can this patch be aplied without hurting C3/C7 CPU's with just
    > > one RNG? Maybe an expert needs to test/answer?
    > > Maybe some logic needs to be applied around the extra bit?
    >
    >>From the padlock spec..
    >
    > "SRC Bits[9:8] Noise source select (I): These bits control the two noise
    > sources on the processor that input bits to the accumulation buffers.
    > On Nehemiah processors prior to stepping 8, these bits are reserved
    > and undefined. The default RESET state is both bits = 0."
    >
    > Something like this perhaps ?

    Yes, I think that's a big step in the right direction!

    But I am no expert and cannot really judge how necessary or correct the
    implementation is w.r.t. the 'undefined' function bits for CPU's that
    lack a certain feature.
    -
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