[lkml]   [2007]   [Oct]   [9]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    Timur Tabi <> writes:

    > Yeah, I read that article some time ago when trying to diagnose the
    > problem I was seeing. It does explain the point I'm trying to make.
    > We have a device that's used on two product lines: one ARM-based, and
    > one PowerPC. The ARM is little-endian, and the PowerPC is big-endian.
    > The device can support little-endian or big-endian data, as long as
    > the bit-order matches the byte-order.

    There is no such thing as bit-order. The data lines are numbered,
    say, D0 - D31, with D0 being LSB (bit) and D31 MSB.

    You usually write register bits from MSB to LSB, so shift left
    increments and shift right decrements the value. This is orthogonal
    to the big/little-endianness.

    Now your device can be connected straight to the bus or the data
    lanes (4 on 32-bit PCI) can be crossed. This is platform-dependent.
    The kernel provides functions/macros to access devices in
    a independent way, such as writel/readl/pci_map_* etc.
    Krzysztof Halasa
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    More majordomo info at
    Please read the FAQ at

     \ /
      Last update: 2007-10-09 20:53    [W:0.018 / U:30.004 seconds]
    ©2003-2017 Jasper Spaans. hosted at Digital OceanAdvertise on this site