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    SubjectRe: [PATCH] i386: fix TSC clock source calibration error
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    On Tue, 2007-10-16 at 10:50 -0400, Dave Johnson wrote:
    >
    > range of tsc_khz # of boots % of boots
    > ----------------- ---------- ----------
    > < 1999750 0 0.000%
    > 1999750 - 1999800 21 3.048%
    > 1999800 - 1999850 166 24.128%
    > 1999850 - 1999900 241 35.029%
    > 1999900 - 1999950 211 30.669%
    > 1999950 - 2000000 42 6.105%
    > 2000000 - 2000000 0 0.000%
    > 2000050 - 2000100 0 0.000%
    > [...]
    > 2000100 - 2015000 1 0.145% << BAD
    > 2015000 - 2030000 6 0.872% << BAD
    > 2030000 - 2045000 1 0.145% << BAD
    > 2045000 < 0 0.000%
    >
    > The worst boot was 2032.577 Mhz, over 1.5% off!

    Can you tell us what type of machine this was? I've seen complaints
    where the SMI's can cause some other funny stuff with calibration , be
    no one can every reproduce anything..

    Daniel

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