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    SubjectRe: LFENCE instruction (was: [rfc][patch 3/3] x86: optimise barriers)
    On Wed, Oct 17, 2007 at 01:51:17PM +0800, Herbert Xu wrote:
    > Nick Piggin <> wrote:
    > >
    > > Also, for non-wb memory. I don't think the Intel document referenced
    > > says anything about this, but the AMD document says that loads can pass
    > > loads (page 8, rule b).
    > >
    > > This is why our rmb() is still an lfence.
    > BTW, Xen (in particular, the code in drivers/xen) uses mb/rmb/wmb
    > instead of smp_mb/smp_rmb/smp_wmb when it accesses memory that's
    > shared with other Xen domains or the hypervisor.
    > The reason this is necessary is because even if a Xen domain is
    > UP the hypervisor might be SMP.
    > It would be nice if we can have these adopt the new SMP barriers
    > on x86 instead of the IO ones as they currently do.

    That's a good point actually. Something like raw_smp_*mb, which
    always orders memory, but only for regular WB operatoins. I could
    put that on the todo list...

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      Last update: 2007-10-17 14:31    [W:0.018 / U:4.656 seconds]
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