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SubjectRe: LFENCE instruction
On Tue, 16 Oct 2007, H. Peter Anvin wrote:

> Mikulas Patocka wrote:
> >
> > PREFETCH* doesn't change program semantics. The processor is allowed to
> > ignore prefetch instruction if it doesn't have resources needed for
> > prefetch. It not ordered wrt. fences.
> >
> > PREFETCHNTA was implemented as prefetch into L1 cache and omitting L2 cache
> > on Pentium 3 and M --- and it is implemented as prefetch into L2 cache on
> > other --- do it doesn't really use any special buffers.
> >
>
> It's semantics allows it to, though. It's not clear to me whether it is
> actually necessary on existing chips.
>
> It does, I believe, way-restricted prefetch on existing silicon.

It is allowed to use special buffers for prefetch, but --- because
prefetch doesn't change program semantics, these special buffers must be
kept consistent just like caches --- they must be snooped for bus
transactions and they must be checked each time something writes to cache.

So I doubt anyone will ever implement it this way --- it's too much
silicon for too little effect.

Mikulas

> -hpa
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