Messages in this thread | | | From | Andi Kleen <> | Subject | Re: data corruption with nvidia chipsets and IDE/SATA drives (k8 cpu errata needed?) | Date | Fri, 19 Jan 2007 09:49:47 +1100 |
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On Friday 19 January 2007 08:57, Chip Coldwell wrote:
> But it still might be a reasonable thing to do to test the theory that > the problem is cache coherency across the graphics aperture, even if > it isn't a long-term solution for the problem.
I suspect it would disturb timing so badly that it might hide the original problem. If that is true then adding udelays might hide it too.
Ok i guess you could test with a UP kernel. There change_page_attr should be much cheaper because it doesn't need to IPI to other CPUs. Also use a .2.6.20-rc* kernel that uses CLFLUSH in there, not WBINVD which is also very costly.
Anyways I guess we can just wait what the hardware people figure out.
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