Messages in this thread |  | | | Subject | Re: TG3 data corruption (TSO ?) | | From | Benjamin Herrenschmidt <> | | Date | Sun, 10 Sep 2006 11:17:32 +1000 |
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> > semantics. At least what is implemented currently on PowerPC is the > > __raw_* versions which not only have no barriers at all (they don't even > > order between MMIOs, for example, readl might cross writel), and do no > > endian swap. Quite a mess of semantics if you ask me... Then there has > > __writel/__readl seems more in keeping for just not locking.
Not locking... you mean not ordering I suppose. Ok, so the question is no ordering at all (that is even between MMIO read/writes, thus a __readl can cross a __writel), or just no ordering between MMIO and cacheable storage ?
It's an important difference and both have their use. For example, on PowerPC, if I completely remove barriers, I get the first semantic and I get the ability to write combine on non-cacheable storage as a benefit (provided we add an ioremap_wc or such, as the Guarded bit we set on normal non-cacheable space does also prevent write combining on most implementations). However, if I keep at least ordering between MMIOs, then I leave an eieio in there, which is not nearly as expensive than a full sync but will not order cacheable cs. non-cacheable. However, it will also prevent write combine as far as I remember.
Ben.
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