Messages in this thread | | | Subject | Re: question regarding cacheline size | From | Arjan van de Ven <> | Date | Thu, 07 Sep 2006 14:33:25 +0200 |
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> > So I think we should redo the PCI subsystem to set cacheline size during > the buswalk rather than waiting for drivers to ask for it to be set.
... while allowing for quirks for devices that go puke when this register gets written ;)
(afaik there are a few)
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