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    SubjectRe: question regarding cacheline size
    Matthew Wilcox wrote:
    > Just call pci_set_mwi(), that'll make sure the cache line size is set
    > correctly.

    Sounds simple enough. Just two small worries though.

    * It has an apparent side effect of setting PCI_COMMAND_INVALIDATE,
    which should be okay in sil3124's case.

    * The controller might have some restrictions on configurable cache line
    size. This is the same for MWI, so I guess this problem is just imaginary.

    For the time being, I'll go with pci_set_mwi() but IMHO it would be
    better to have a pci helper for this purpose -
    pci_config_cacheline_size() or something.


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