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Subject[patch 17/37] TG3: Disable TSO by default
-stable review patch.  If anyone has any objections, please let us know.

------------------
From: Michael Chan <mchan@broadcom.com>

Disable TSO by default on some chips due to hardware errata.

Enabling TSO can lead to tx timeouts in some cases when the TSO
header size exceeds 80 bytes on the affected chips. This limit
can be exceeded when the TCP header contains the timestamp option
plus 2 SACK blocks, for example. A more complete workaround is
available in the next 2.6.18 kernel.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>


---
drivers/net/tg3.c | 12 ++++++++----
drivers/net/tg3.h | 1 +
2 files changed, 9 insertions(+), 4 deletions(-)
--- linux-2.6.17.11.orig/drivers/net/tg3.c
+++ linux-2.6.17.11/drivers/net/tg3.c
@@ -69,8 +69,8 @@

#define DRV_MODULE_NAME "tg3"
#define PFX DRV_MODULE_NAME ": "
-#define DRV_MODULE_VERSION "3.59"
-#define DRV_MODULE_RELDATE "June 8, 2006"
+#define DRV_MODULE_VERSION "3.59.1"
+#define DRV_MODULE_RELDATE "August 25, 2006"

#define TG3_DEF_MAC_MODE 0
#define TG3_DEF_RX_MODE 0
@@ -11381,11 +11381,15 @@ static int __devinit tg3_init_one(struct
tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
}

- /* TSO is on by default on chips that support hardware TSO.
+ /* TSO is on by default on chips that support HW_TSO_2.
+ * Some HW_TSO_1 capable chips have bugs that can lead to
+ * tx timeouts in some cases when TSO is enabled.
* Firmware TSO on older chips gives lower performance, so it
* is off by default, but can be enabled using ethtool.
*/
- if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
+ if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
+ tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2))
dev->features |= NETIF_F_TSO;

#endif
--- linux-2.6.17.11.orig/drivers/net/tg3.h
+++ linux-2.6.17.11/drivers/net/tg3.h
@@ -125,6 +125,7 @@
#define CHIPREV_ID_5750_A0 0x4000
#define CHIPREV_ID_5750_A1 0x4001
#define CHIPREV_ID_5750_A3 0x4003
+#define CHIPREV_ID_5750_C2 0x4202
#define CHIPREV_ID_5752_A0_HW 0x5000
#define CHIPREV_ID_5752_A0 0x6000
#define CHIPREV_ID_5752_A1 0x6001
--
-
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