Messages in this thread | | | Subject | Re: Flushing writes to PCI devices | From | Bryan O'Sullivan <> | Date | Thu, 21 Sep 2006 14:04:00 -0700 |
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On Thu, 2006-09-21 at 13:56 -0700, Roland Dreier wrote: > Bryan> Yes. If your device requires that writes to some locations > Bryan> in MMIO space be performed in a specific order, you must > Bryan> explicitly do this in your driver. Intel CPUs will flush > Bryan> posted writes out of order, for example. > > Really? Just normal posted PCI writes without using MTRRs or > write-combining or anything like that?
No, not normal writes, but if you're writing to an area where you've enabled write combining, it will happen (but not IIRC on AMD x86_64 CPUs). Sorry for the lack of clarity.
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