lkml.org 
[lkml]   [2006]   [Sep]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: Flushing writes to PCI devices
From
Date
    Bryan> Yes.  If your device requires that writes to some locations
Bryan> in MMIO space be performed in a specific order, you must
Bryan> explicitly do this in your driver. Intel CPUs will flush
Bryan> posted writes out of order, for example.

Really? Just normal posted PCI writes without using MTRRs or
write-combining or anything like that?

That doesn't seem right to me, and I would expect all sorts of things
to break if it were true.

- R.
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2006-09-21 22:59    [W:0.066 / U:0.396 seconds]
©2003-2011 Jasper Spaans. Advertise on this site