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    SubjectRe: Uses for memory barriers
    On Wed, Sep 20, 2006 at 04:48:45AM +1000, Nick Piggin wrote:
    > Paul E. McKenney wrote:
    > >On Wed, Sep 20, 2006 at 03:51:29AM +1000, Nick Piggin wrote:
    > >>If store forwarding is able to occur outside cache coherency protocol,
    > >>then I don't see why not. I would also be interested to know if this
    > >>is the case on real systems.
    > >
    > >
    > >We are discussing multiple writes to the same variable, correct?
    > >
    > >Just checking...
    > Correct.

    I am having a hard time seeing how this would happen.

    Sooner or later, the cacheline comes to the store queue, defining
    the ordering. All changes that occurred in the store queue while
    waiting for the cache line appear to other CPUs as having happened
    in very quick succession while the cacheline resides with the store
    queue in question.

    So, what am I missing?

    Thanx, Paul
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      Last update: 2006-09-19 21:37    [W:0.026 / U:0.140 seconds]
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