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SubjectRe: [RFC] MMIO accessors & barriers documentation #2


On Mon, 18 Sep 2006, Benjamin Herrenschmidt wrote:
>
> Class 1: Ordered accessors
> --------------------------
>
> 1- {read,write}{b,w,l,q} : MMIO accessors. Those accessors provide
> all MMIO ordering requirements. They are thus called "fully ordered".
> That is #1, #2 and #4 for writes and #1 and #3 for reads.

Well, it's already not defined to be #4 right now on SGI boxes, and we
have that (badly named) mmiowb() thing to enforce #4, so I think we should
just accept that write[bwl]() it's _that_ ordered.

And on x86, we _already_ depend on "wmb()" to be a "normal write to MMIO
write" barrier, which is technically wrong and bad. Again, thanks to
mmiowb(), normal memory accesses and MMIO accesses have already been
defined to not be in the same "ordering domain", so "wmb()" is technically
wrong and may not order a regular write wrt a MMIO (because it doesn't do
so for the other order: MMIO->spin_unlock).

So I think we should just admit that at least MMIO _stores_ are already
not entirely ordered, and not try to strengthen the rules for the current
setup (and just try to clarify the currently accepted semantics).

Linus
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