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    SubjectRe: Uses for memory barriers
    Paul E. McKenney <> wrote:

    > 2. All stores to a given single memory location will be perceived
    > as having occurred in the same order by all CPUs.

    Does that take into account a CPU combining or discarding coincident memory

    For instance, a CPU asked to issue two writes to the same location may discard
    the first if it hasn't done it yet.

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      Last update: 2006-09-12 19:19    [W:0.018 / U:17.132 seconds]
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