[lkml]   [2006]   [Jul]   [30]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: REGRESSION: the new i386 timer code fails to sync CPUs
On Sun, 2006-07-30 at 23:13 +0200, Matthias Urlichs wrote:
> Hi,
> Andi Kleen:
> > > It is a "CPU0: Intel(R) Xeon(TM) CPU 3.00GHz stepping 03".
> >
> > Was that on that system? I guess it could be checked for and TSC
> > be forced off. It sounds like a real CPU bug however.
> >
> Board problem? After all, it has some very noxious DMI entries:
> System Information
> Manufacturer: Intel Corporation
> Product Name: Nocona/Tumwater Customer Reference Board
> Version: Revision A0
> Serial Number: 0123456789
> UUID: 0A0A0A0A-0A0A-0A0A-0A0A-0A0A0A0A0A0A
> ... all of which are patently *wrong*.
> You'd have to ask the people from Tyan what the hell they were smoking
> when they blindly copied the Intel data.
> At least the different CPU speed issue is a known bug, fixed by a
> BIOS update. I'll postpone that until we have a working kernel fix,
> for obvious reasons.

if the hardware side is different *speed*.. then a tsc sync ain't going
to work... sure we write to it but it's immediately out of sync again

if you want to mail me at work (you don't), use arjan (at)

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

 \ /
  Last update: 2006-07-30 23:23    [from the cache]
©2003-2014 Jasper Spaans. hosted at Digital Ocean