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    SubjectRe: REGRESSION: the new i386 timer code fails to sync CPUs
    On 30 Jul 2006 22:10:05 +0200
    Andi Kleen <> wrote:

    > > I guess Matthias didn't test this patch. Can we get some obviously-correct
    > > fix in place for 2.6.18?
    > So far we don't have any idea what the problem is on that system.

    I believe we do know what the problem is: a) write_tsc() doesn't work, b)
    the TSC's are unsynced (or have an offset), c) we removed a check which
    would have caused pmtmr/rtc fallback.

    > > It is a "CPU0: Intel(R) Xeon(TM) CPU 3.00GHz stepping 03".
    > Was that on that system?


    > I guess it could be checked for and TSC
    > be forced off.

    There's no need for that, I think. synchronize_tsc_bp() knows for-sure
    that the synchronization failed, in a way which works on all CPUs.

    So all we need to do is to set some flag in synchronize_tsc_bp() if `buggy'
    is set, telling the clocksource code to give up on the TSC.

    > It sounds like a real CPU bug however.

    I was hoping the Intel guys could help out with that.
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      Last update: 2006-07-30 23:01    [W:0.021 / U:4.208 seconds]
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