Messages in this thread | | | Date | Sun, 30 Jul 2006 13:55:18 -0700 | From | Andrew Morton <> | Subject | Re: REGRESSION: the new i386 timer code fails to sync CPUs |
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On 30 Jul 2006 22:10:05 +0200 Andi Kleen <ak@muc.de> wrote:
> > I guess Matthias didn't test this patch. Can we get some obviously-correct > > fix in place for 2.6.18? > > So far we don't have any idea what the problem is on that system.
I believe we do know what the problem is: a) write_tsc() doesn't work, b) the TSC's are unsynced (or have an offset), c) we removed a check which would have caused pmtmr/rtc fallback.
> > It is a "CPU0: Intel(R) Xeon(TM) CPU 3.00GHz stepping 03". > > Was that on that system?
yes.
> I guess it could be checked for and TSC > be forced off.
There's no need for that, I think. synchronize_tsc_bp() knows for-sure that the synchronization failed, in a way which works on all CPUs.
So all we need to do is to set some flag in synchronize_tsc_bp() if `buggy' is set, telling the clocksource code to give up on the TSC.
> It sounds like a real CPU bug however.
I was hoping the Intel guys could help out with that. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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