Messages in this thread Patch in this message | | | From | Kirill Smelkov <> | Subject | [PATCH] doc: fix typos in Documentation/memory-barriers.txt | Date | Wed, 21 Jun 2006 11:20:55 +0400 |
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Thanks for excellent article! While reading it I discovered a few typos.
Signed-off-by: Kirill Smelkov <kirr@mns.spb.ru>
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 4710845..638b686 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -282,7 +282,7 @@ Memory barriers come in four basic varie A write barrier is a partial ordering on stores only; it is not required to have any effect on loads. - A CPU can be viewed as as commiting a sequence of store operations to the + A CPU can be viewed as commiting a sequence of store operations to the memory system as time progresses. All stores before a write barrier will occur in the sequence _before_ all the stores after the write barrier. @@ -484,7 +484,7 @@ lines. The pointer P might be stored in variable B might be stored in an even-numbered cache line. Then, if the even-numbered bank of the reading CPU's cache is extremely busy while the odd-numbered bank is idle, one can see the new value of the pointer P (&B), -but the old value of the variable B (1). +but the old value of the variable B (2). Another example of where data dependency barriers might by required is where a @@ -744,7 +744,7 @@ some effectively random order, despite t : : -If, however, a read barrier were to be placed between the load of E and the +If, however, a read barrier were to be placed between the load of B and the load of A on CPU 2: CPU 1 CPU 2 @@ -1461,7 +1461,7 @@ instruction itself is complete. On a UP system - where this wouldn't be a problem - the smp_mb() is just a compiler barrier, thus making sure the compiler emits the instructions in the -right order without actually intervening in the CPU. Since there there's only +right order without actually intervening in the CPU. Since there's only one CPU, that CPU's dependency ordering logic will take care of everything else. @@ -1640,7 +1640,7 @@ functions: The PCI bus, amongst others, defines an I/O space concept - which on such CPUs as i386 and x86_64 cpus readily maps to the CPU's concept of I/O - space. However, it may also mapped as a virtual I/O space in the CPU's + space. However, it may also be mapped as a virtual I/O space in the CPU's memory map, particularly on those CPUs that don't support alternate I/O spaces.
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