Messages in this thread | | | Subject | Re: cacheline alignment and per-cpu data | From | Jes Sorensen <> | Date | 12 Jun 2006 05:17:53 -0400 |
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>>>>> "Chase" == Chase Venters <chase.venters@clientec.com> writes:
Chase> On Fri, 9 Jun 2006, Chris Friesen wrote: >> Will this cause cacheline pingpong? If I do this sort of thing do >> I need to ensure that the struct is a multiple of cacheline size >> (or specify cacheline alignement)?
Chase> Yes. If CPU 2 tries to write to struct member 1 of array Chase> element 2, and array element 1 is in CPU 1's cache, it must be Chase> invalidated.
Chase> GCC (and kernel macros) provide good support for enforced Chase> cacheline alignment, but it's also possible to pad your Chase> structures.
Best way to go is to use __cacheline_aligned rather than try to get the padding right manually. Someone will add a field somewhere in the middle and mess it up and nobody notices.
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