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    SubjectRe: [PATCH] Document Linux's memory barriers
    Hi!

    > +There are some more advanced barriering functions:
    > +
    > + (*) set_mb(var, value)
    > + (*) set_wmb(var, value)
    > +
    > + These assign the value to the variable and then insert at least a write
    > + barrier after it, depending on the function.
    > +

    I... don't understand what these do. Better explanation would
    help.. .what is function?

    Does it try to say that set_mb(var, value) is equivalent to var =
    value; mb(); but here mb() affects that one variable, only?


    > +In all cases there are variants on a LOCK operation and an UNLOCK operation.
    > +
    > + (*) LOCK operation implication:
    > +
    > + Memory accesses issued after the LOCK will be completed after the LOCK
    > + accesses have completed.

    "LOCK access"? Does it try to say that ...will be completed after any
    access inside lock region is completed?

    ("LOCK" looks very much like well-known i386 prefix. Calling it
    *_lock() or something would avoid that confusion. Fortunately there's
    no UNLOCK instruction :-)

    > + (*) UNLOCK operation implication:
    > +
    > + Memory accesses issued before the UNLOCK will be completed before the
    > + UNLOCK accesses have completed.
    > +
    > + Memory accesses issued after the UNLOCK may be completed before the UNLOCK
    > + accesses have completed.
    > +
    > + (*) LOCK vs UNLOCK implication:
    > +
    > + The LOCK accesses will be completed before the unlock accesses.
    ~~~~~~
    capital? Or
    lower it everywhere?


    > +==============================
    > +I386 AND X86_64 SPECIFIC NOTES
    > +==============================
    > +
    > +Earlier i386 CPUs (pre-Pentium-III) are fully ordered - the operations on the
    > +bus appear in program order - and so there's no requirement for any sort of
    > +explicit memory barriers.
    > +
    > +From the Pentium-III onwards were three new memory barrier instructions:
    > +LFENCE, SFENCE and MFENCE which correspond to the kernel memory barrier
    > +functions rmb(), wmb() and mb(). However, there are additional implicit memory
    > +barriers in the CPU implementation:
    > +
    > + (*) Normal writes imply a semi-rmb(): reads before a write may not complete
    > + after that write, but reads after a write may complete before the write
    > + (ie: reads may go _ahead_ of writes).

    This makes it sound like pentium-III+ is incompatible with previous
    CPUs. Is it really the case?
    Pavel
    --
    Web maintainer for suspend.sf.net (www.sf.net/projects/suspend) wanted...
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