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    SubjectRe: Memory barriers and spin_unlock safety
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    On Friday 03 March 2006 15:06, Benjamin Herrenschmidt wrote:
    > The main problem I've had in the past with the ppc barriers is more a
    > subtle thing in the spec that unfortunately was taken to the word by
    > implementors, and is that the simple write barrier (eieio) will only
    > order within the same storage space, that is will not order between
    > cacheable and non-cacheable storage.

    I've heard Sparc has the same issue... in which case it may not be a "chip
    designer was too literal" thing, but rather it really simplifies chip
    implementation to do it that way.

    --
    Hollis Blanchard
    IBM Linux Technology Center
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