Messages in this thread | | | Subject | Re: [PATCHSET] block: fix PIO cache coherency bug | From | James Bottomley <> | Date | Thu, 02 Mar 2006 14:43:59 -0600 |
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On Thu, 2006-03-02 at 20:30 +0000, Russell King wrote: > Your understanding of the problem on ARM remains fundamentally flawed. > I see no way to resolve this since you don't seem to listen or accept > my reasoning.
You have advanced no reason for using flush_dcache_page() instead of flush_kernel_dcache_page() except this:
> ISTR davem recommended flush_dcache_page() be used for this.
and this:
> 2. (this is my own) The cachetlb document specifies quite clearly > what > is required whenever a page cache page is written to - that is > flush_dcache_page() is called. The situation when a driver uses > PIO > quote clearly violates the requirements set out in that document. >
Your problem, as you state:
> However, in the PIO case, there is the possibility that the data > read > from the device into the kernel mapping results in cache lines > associated with the page. Moreover, if the cache is > write-allocate, > you _will_ have cache lines. > > Therefore, you have two completely differing system states > depending > on how the driver decided to transfer data from the device to the > page > cache.
It is my contention that flush_kernel_dcache_page() ejects the cache lines that may be dirty in the kernel mapping and makes the underlying memory coherent again. This is the same net effect as a DMA transfer (data in memory but not in kernel cache).
> Therefore, message I'm getting from you is that we are not allowed to > have an ARM system which can possibly work correctly with PIO. > > As a result, I have no further interest in trying to resolve this issue, > period. ARM people will just have to accept that PIO mode IDE drivers > just will not be an option.
Could you actually address the argument instead of getting all huffy?
James
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