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    Subject[PATCH] AMD64: fix mce_cpu_quirks typos
    Date
    The spurious MCE is TLB-related.  I *think* the bit for the correct
    status code is stored at position 10 HEX, not 10 DEC. At least I
    still get those MCEs on a two-way Opteron box, even though they are
    supposed to be filtered out.

    Signed-off-by: Florian Weimer <fw@deneb.enyo.de>

    ---

    arch/x86_64/kernel/mce.c | 4 ++--
    1 files changed, 2 insertions(+), 2 deletions(-)

    102dfead12550ecaf7363a8ca7269ac0f1241bac
    diff --git a/arch/x86_64/kernel/mce.c b/arch/x86_64/kernel/mce.c
    index 13a2ead..975d128 100644
    --- a/arch/x86_64/kernel/mce.c
    +++ b/arch/x86_64/kernel/mce.c
    @@ -350,9 +350,9 @@ static void __cpuinit mce_cpu_quirks(str
    {
    /* This should be disabled by the BIOS, but isn't always */
    if (c->x86_vendor == X86_VENDOR_AMD && c->x86 == 15) {
    - /* disable GART TBL walk error reporting, which trips off
    + /* disable GART TLB walk error reporting, which trips off
    incorrectly with the IOMMU & 3ware & Cerberus. */
    - clear_bit(10, &bank[4]);
    + clear_bit(0x10, &bank[4]);
    /* Lots of broken BIOS around that don't clear them
    by default and leave crap in there. Don't log. */
    mce_bootlog = 0;
    --
    1.1.5
    -
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