Messages in this thread | | | Date | Sun, 24 Dec 2006 11:16:22 -0800 | From | Randy Dunlap <> | Subject | Re: [PATCH] Update Documentation/pci.txt v7 |
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On Sat, 23 Dec 2006 23:07:26 -0700 Grant Grundler wrote:
> +10. Legacy I/O port free driver > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
That subject (and patches with similar subject) confuses me. It's difficult to associate the adjectives correctly. I suppose it just needs some hyphens/dashes, like:
10. Legacy-I/O-port-free driver
but that's ETOOMUCH. Maybe ?
10. Stop using legacy I/O space
> +Large servers may not be able to provide I/O port resources to all PCI > +devices. I/O Port space is only 64KB on Intel Architecture[1] and is > +likely also fragmented since the I/O base register of PCI-to-PCI > +bridge will usually be aligned to a 4KB boundary[2]. On such systems, > +pci_enable_device() and pci_request_region() will fail when > +attempting to enable I/O Port regions that don't have I/O Port > +resources assigned.
> +11. MMIO Space and "Write Posting" > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > +Converting a driver from using I/O Port space to using MMIO space > +often requires some additional changes. Specifically, "write posting" > +needs to be handled. Many drivers (e.g. tg3, acenic, sym53c8xx_2) > +already do this. I/O Port space guarantees write transactions reach the PCI > +device before the CPU can continue. Writes to MMIO space allow the CPU > +to continue before the transaction reaches the PCI device. HW weenies > +call this "Write Posting" because the write completion is "posted" to > +the CPU before the transaction has reached its destination. > + > +Thus, timing sensitive code should add readl() where the CPU is > +expected to wait before doing other work. The classic "bit banging" > +sequence works fine for I/O Port space: > + > + for (i=8; --i; val >>= 1) {
Please use: i = 8; to match CodingStyle. (and below)
> + outb(val & 1, ioport_reg); /* write bit */ > + udelay(10); > + } > + > +The same sequence for MMIO space should be: > + > + for (i=8; --i; val >>= 1) { > + writeb(val & 1, mmio_reg); /* write bit */ > + readb(safe_mmio_reg); /* flush posted write */ > + udelay(10); > + }
Rest looks good to me.
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