Messages in this thread | | | Date | Sat, 21 Oct 2006 22:13:45 -0700 | From | "Yinghai Lu" <> | Subject | Re: [PATCH] x86-64: typo in __assign_irq_vector when updating pos for vector and offset |
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On 10/21/06, Muli Ben-Yehuda <muli@il.ibm.com> wrote: > On Sat, Oct 21, 2006 at 09:00:17PM +0000, Linux Kernel Mailing List wrote: > Booting processor 1/4 APIC 0x1 > Initializing CPU#1 > Calibrating delay using timer specific routine.. 6339.07 BogoMIPS (lpj=12678150)CPU: Trace cache: 12K uops, L1 D cache: Initializing CPU#2 > Calibrating delay using timer specific routine.. 6339.11 BogoMIPS (lpj=12678228)CPU: Trace cache: 12K uops, L1 D cache: 16K > CPU: L2 cache: 1024K > CPU: Physical Processor ID: 3 > CPU: Processor Core ID: 0 > CPU2: Thermal monitoring enabled (TM1) > Intel(R) Pentium(R) 4 CPU 3.16GHz stepping 09 > lockdep: not fixing up alternatives. > Booting processor 3/4 APIC 0x7 > Initializing CPU#3 > Calibrating delay using timer specific routine.. 6339.20 BogoMIPS (lpj=12678401)CPU: Trace cache: 12K uops, L1 D cache: 16K > CPU: L2 cache: 1024K > CPU: Physical Processor ID: 3 > CPU: Processor Core ID: 0 > CPU3: Thermal monitoring enabled (TM1) > Intel(R) Pentium(R) 4 CPU 3.16GHz stepping 09 > Brought up 4 CPUs
It seems it tried to initialize CPU2, before CPU1 is all set.
current code still initialize CPU one by one, because there is some share data structure.
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