Messages in this thread | | | Subject | Re: [PATCHSET] block: fix PIO cache coherency bug | From | James Bottomley <> | Date | Fri, 13 Jan 2006 22:58:50 -0600 |
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On Fri, 2006-01-13 at 14:43 -0800, David S. Miller wrote: > Not true, VIPT caches participate in cache coherency transactions > with the PCI host controller (and thus the PCI device), whereas > VIVT caches do not.
Yes ... I understand that. However for VIPT caches, we can only specify one Virtual Index to be coherent (and the user mappings and the kernel are at different virtual indexes) so we specify the kernel mapping in the current implementation. We rely on the page cache cache<->user piece making the rest of the user mappings coherent. So on parisc we come out of the dma_unmap with the kernel coherent but not userspace. The content of these patches was to put a flush_dcache_page() in the PIO path, which makes both kernel and user mappings fully coherent. If there was a bug because that is necessary, then it should show up on the VIPT machines like parisc because user space isn't currently coherent after a dma_unmap. But like I asked, is there a pointer to the original bug ... I really think I need to look at that.
> It does make a big difference, it's very hard to share datastructures > with a device concurrently accessing them (what we call PCI consistent > DMA mappings) on a VIVT cache.
Yes ... I've always fancied a VIVT machine to play with ... but no-one's ever sent me such a toy, sigh.
James
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