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SubjectRe: [PATCHSET] block: fix PIO cache coherency bug
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On Fri, 2006-01-13 at 22:02 +0000, Russell King wrote:
> Unfortunately, as I previously explained, I'm not able to test this.
> The reason is that in order to reproduce the bug, you need a system
> with a VIVT write-back write-allocate cache.
>
> Unfortunately, the few systems I have which have such a cache do not
> have IDE, SCSI nor SATA (not even PCMCIA.) I suggest contacting the
> folk who reported the bug in the first instance.

Could someone explain (or give a reference to) the actual problem? If
it's a cache coherency issue it should show up with VIPT arhictectures
as well as VIVT ones ... I have access to parisc systems (with SCSI),
which are VIPT.

James


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