Messages in this thread | | | Subject | Re: [PATCHSET] block: fix PIO cache coherency bug | From | James Bottomley <> | Date | Fri, 13 Jan 2006 16:38:49 -0600 |
| |
On Fri, 2006-01-13 at 22:02 +0000, Russell King wrote: > Unfortunately, as I previously explained, I'm not able to test this. > The reason is that in order to reproduce the bug, you need a system > with a VIVT write-back write-allocate cache. > > Unfortunately, the few systems I have which have such a cache do not > have IDE, SCSI nor SATA (not even PCMCIA.) I suggest contacting the > folk who reported the bug in the first instance.
Could someone explain (or give a reference to) the actual problem? If it's a cache coherency issue it should show up with VIPT arhictectures as well as VIVT ones ... I have access to parisc systems (with SCSI), which are VIPT.
James
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |