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    SubjectRe: Dual core Athlons and unsynced TSCs
    On Fri, Jan 13, 2006 at 02:05:23PM -0800, David Lang wrote:
    > On Fri, 13 Jan 2006 wrote:
    > >On Fri, Jan 13, 2006 at 01:18:35PM -0800, David Lang wrote:
    > >>Lee, the last time I saw this discussion I thought it was identified that
    > >>the multiple cores (or IIRC the multiple chips in a SMP motherboard) would
    > >>only get out of sync when power management calls were made (hlt or
    > >>switching the c-state). IIRC the workaround that was posted then was to
    > >>just disable these in the kernel build.
    > >
    > >not using 'hlt' when idling means that you spend 10s of Watts more power
    > >on mostly idle systems.
    > true, but for people who need better time accruacy then the other
    > workaround this may be very acceptable.

    sure, if power doesn't matter use idle=poll => problem solved.
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      Last update: 2006-01-13 23:16    [W:0.018 / U:82.492 seconds]
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