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SubjectRe: [discuss] Re: [PATCH] x86-64: Fix bad assumption that dualcore cpus have synced TSCs
On Tuesday 20 September 2005 23:03, Daniel Jacobowitz wrote:

> FYI, at least I have reproduced this without powernow loaded.

There are cases that we are aware of where the TSC will count slower while the
processor is halted. This can make TSC's get out of sync on dual cores.

I wonder if you can reproduce this problem while also running a pair of cpu
bound tasks on your dual core box. If you can't, then this is the culprit.

In general, however, on multisocket systems, you can't depend on TSC's being
synchronized between sockets, so all of this is moot. We just have to deal
with it.

Ray Bryant
AMD Performance Labs Austin, Tx
512-602-0038 (o) 512-507-7807 (c)

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