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SubjectRe: [PATCH 2/5] atomic: introduce atomic_inc_not_zero
Roman Zippel wrote:
> Hi,
>
> On Thu, 15 Sep 2005, Nick Piggin wrote:
>
>
>>Also needs work on those same architectures. Other architectures
>>might want to look at providing a more optimal implementation.
>
>
> IMO a rather pointless primitive, unless there is a cpu architecture which
> has a inc_not_zero instruction, otherwise it will always be the same as
> using cmpxchg.
>

It will always be *implemented* with cmpxchg you mean, which is a
bit different. But even then, no, you definitely don't need an
inc_not_zero instruction to make this primitive faster than the
cmpxchg version. Just look at all the !SMP architectures that just
turn off interrupts while doing the op. Look at the architectures
that use hashed spinlocks.

Or here is possible pseudo code for an architecture with ll/sc
instructions:

do {
tmp = load_locked(v);
if (!tmp)
break;
tmp++;
} while (!store_cond(v, tmp));
return tmp;

As opposed to using the cmpxchg version, which would have more
loads and conditional branches, AFAIKS.

--
SUSE Labs, Novell Inc.

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