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SubjectRe: question on memory barrier
On Fri, 26 Aug 2005, moreau francis wrote:

> I don't think that MIPS cpu reorder memory access, but gcc can ! And I
> don't think that the use of 'volatile' can prevent it to do that.

Well, certain MIPS implementations may merge multiple uncached writes in
the writeback buffer, e.g. writes to different bytes within a single
aligned word. This is true for consecutive writes; I'm not sure this
permits jumping the writeback queue, though.

> > To return to the point directly at hand - on MIPS architectures to date,
> > simply doing your memory access through a "volatile u32 *" is sufficient
> > to ensure that the IO hits the bus (assuming that your pointer points to
> > kseg1, not kseg0, or is otherwise uncached), because 'volatile' forces
> > gcc to generate a "sw" for each store, and all MIPS so far have been
> > designed so that multiple uncached writes to mmio locations do generate
> > multiple bus transactions.

Unfortunately this is not true -- see above. This is why even wmb()
isn't a no-op on MIPS.

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