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SubjectRe: question on memory barrier
On Mer, 2005-08-24 at 12:53 -0700, Jesse Barnes wrote:
> writel() ensures ordering? Only from one CPU, another CPU issuing a
> write at some later time may have its write arrive first. See
> Documentation/io_ordering.txt for some documentation I put together on
> this issue.

And in more detail from the deviceiobook..

In addition to write posting, on some large multiprocessing
(e.g. SGI Challenge, Origin and Altix machines) posted writes
be strongly ordered coming from different CPUs. Thus it's
to properly protect parts of your driver that do memory-mapped
with locks and use the <function>mmiowb</function> to make sure
arrive in the order intended. Issuing a regular <function>readX
</function> will also ensure write ordering, but should only be
when the driver has to be sure that the write has actually
at the device (not that it's simply ordered with respect to
writes), since a full <function>readX</function> is a relatively
expensive operation.

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